Revolutionizing the Design Flow of Digital Circuits for High Performance and Efficiency

Are you ready to learn about cutting-edge technology that is revolutionizing the way we design digital circuits? Say hello to FPGAs - the Swiss Army knife of computer chips!

FPGAs, or Field-Programmable Gate Arrays, are integrated circuits that can be programmed and reprogrammed to perform a vast array of digital functions. They are like a canvas for designers to create custom circuits that are tailor-made for their specific needs. With FPGAs, you do not need to create an entirely new chip for each application. Instead, you simply reprogram the FPGA to adapt to new tasks. The significance of FPGAs lies in their high degree of customization and flexibility and it is used in a broad range of applications, including digital signal processing, communications, automotive, aerospace, and defence industries.

The main challenge with FPGA is the complexity of the design flow. Mapping a design onto an FPGA requires a series of computationally hard steps, resulting in potential degradation of the performance. This design flow can take hours to even days for the largest designs, making small changes to the design a time-consuming and tedious process. The traditional optimization algorithms used to solve these problems have limitations due to their isolation and do not take into account the entire design space.

FPGA Design with Machine Learning and Deep Learning Algorithms

To solve the challenges, Dr. Gary Grewal, from the School of Computer Science and Dr. Shawki Areibi, from the School of Engineering, have turned to machine learning (ML) and deep learning (DL) algorithms to improve the design flow of FPGA. ML and DL are computer programs that can learn to automatically recognize patterns and make predictions or decisions based on data. By using these algorithms, they can optimize the design flow as a whole rather than in isolation, resulting in higher-quality solutions in a shorter amount of time. These advancements in machine learning and deep learning have made it possible to implement artificial intelligence (AI) on FPGAs, making them a more power-efficient alternative to graphics processing units (GPUs) for machine learning and AI applications.

Grewal and his team in their new research have developed computer models, which they call "probes" that can predict how much time, power, and resources will be needed to complete the routing step of the process. Routing is the process of connecting the logical blocks placed on an FPGA chip using a network of wires. So, if the routing step takes too long or uses too many resources, the chip might not work as well as it should, or it might take too long to manufacture. By using these probes, the researchers hope to be able to make changes earlier in the process so that they can improve the final outcome.

Game-Changer performance

“Integrating Machine-Learning probes into the design flow is a game-changer in terms of optimization methods based on AI, and can be used to improve placement algorithms” said Grewal. Additionally, they found that integrating ML probes significantly reduces runtime in the Central processing unit (CPU).

The idea of using machine learning probes has won several awards including two Michal Servit Awards (2018 and 2019) given to the most outstanding paper in the area of design algorithms, methods and CAD tools for FPGAs from one of the most prestigious FGPA conferences in Europe, and more recently the 2022 Symposium on Circuits and Systems Design (SBCCI) Best Track Paper Award.

Having in mind the potential of the concept, by benefiting from the expertise of Timothy Martin and Charlotte Barnes, PhD and undergraduate students from the School of Computer Science, respectively, the research team plans to continue developing ML probes to provide information and feedback, which chips will be used in smart and intelligent ways to make decisions dynamically.

According to Charlotte, “As a child, I found computers and the internet mysterious and incomprehensible, which motivated my pursuit of computer science in university. While the initial magic wore off, my work in the FPGA CAD group has reignited my enthusiasm for the field. Through research, I have gained valuable experience, developed marketable skills, and been exposed to niche technologies, and I hope to continue this work as a graduate student.”

This story was written by Kasra Ghasemi as part of the Science Communicators: Research @ CEPS initiative. Kasra is a PhD candidate in the School of Engineering under Dr.s Syeda Humaira Tasnim and Shohel Mahmud. His research focus is on developing innovative solutions to poor packaging systems and conventional refrigeration methods and their contributions to food waste and global warming – a Latent Heat Thermal Energy Storage system with micro-scale capsules.

Funding Acknowledgement: This work was supported by Natural Sciences and Engineering Research Council of Canada (NSERC) Discovery Grants and an NSERC Postgraduate Scholarship – Doctoral program.

T. Martin, C. Barnes, G. Grewal, and S. Areibi, “Integrating Machine-Learning Probes into the VTR FPGA Design Flow,” in 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI), Aug. 2022, pp. 1–6. doi: 10.1109/SBCCI55532.2022.9893251.